RFIC DESIGN ELEN 351 Lecture 10: RFIC Layout Issues Discussions

Transcription

1 RFIC DESIGN ELEN 351 Lecture 10: RFIC Layout Issues Discussions Dr. Allen Sweet Copy Right 2003 ELEN 351 1

2 LAYOUT PARASITIC ELEMENTS THAT MUST BE INCLUDED BELOW 5 GHz Copy Right 2003 ELEN 351 2

3 ADDITIONAL LAYOUT PARASITIC ELEMENTS ABOVE 5 GHz Copy Right 2003 ELEN 351 3

4 Layout of a Large (A=24) Transistor Copy Right 2003 ELEN 351 4

5 Ballast Resistors in Large Transistors Copy Right 2003 ELEN 351 5

6 Design of Interdigitated Ballast Resistors Copy Right 2003 ELEN 351 6

7 Example of Ballast Resistors Copy Right 2003 ELEN 351 7

8 Blowup of Interdigitated Ballast Resistors Copy Right 2003 ELEN 351 8

9 Metal Migration Causes Metal lines to Fail, limiting Current Copy Right 2003 ELEN 351 9

10 RFIC Technology Comparisons TECHNOLOGY FEATURE SIZE VOLTAGE Ft LINEARITY DEVELOPMENT COST PRODUCTION COST GaAs HBT 2 microns 3 to ex low medium GaAs MESFET.5 microns 5 to good medium high GaAs PHEMT.15 microns 3 to fair medium high SiGe HBT under 1 micron 2 to 4 80 good high low RF CMOS.13 micron 1 to 2 50 good very high very low Copy Right 2003 ELEN

11 Reticle Assembly Add (1/2) Streets to all Circuit Layouts. All Emitter fingers must point in the same direction. Reticle is Assembled by joining the (1/2) streets of all Circuit Layouts, no gaps are allowed. All Layouts, on a Reticle, must share a common Dimension and use two or three options for the second dimension (prefer both to be common). Place test cells for all circuits on the Reticle. PCMs are placed on the Reticle by Foundry. Pizza masks are a very economical for prototypes. Copy Right 2003 ELEN

12 (1/2) Streets are 25 micron PV Lines and 25 micron SPV Lines Copy Right 2003 ELEN

13 Example of a Layout with (1/2) Streets in place Copy Right 2003 ELEN

14 All Homework Assignment Layouts with (1/2) Streets Copy Right 2003 ELEN

15 Device Test Cells with (1/2) Streets in Place Copy Right 2003 ELEN

16 Place all Layouts in Common 1100 X 900 micron (1/2) Streets Copy Right 2003 ELEN

17 1100 X 900 PA Details Copy Right 2003 ELEN

18 1100 X 900 Mixer Details Copy Right 2003 ELEN

19 1100 X 900 Darlington Details Copy Right 2003 ELEN

20 1100 X 900 Feedback Amps, LNA, and VCO Details Copy Right 2003 ELEN

21 1100 X 900 Device Test Cell Details Copy Right 2003 ELEN

22 14,300 X 14,400 micron Reticle: 13 X 16 Die Array, 208 Total Die Copy Right 2003 ELEN

23 Street Details Near PCM Copy Right 2003 ELEN

24 Blowup of Street Details Copy Right 2003 ELEN

25 A Reticle is Stepped Across the Wafer Max Reticle Size: 15 mm x 15 mm Copy Right 2003 ELEN

26 Foundry Costs: InGaP HBT Design Rules: 3-5 k Training: k DRC: 3 10 k Masks: k Engineering wafer run (4 wafers): k Production wafer runs: 3-4 k per wafer for 4 inch, 7-8 k per wafer for 6 inch. Pizza Masks: 5 k 15 k for a 5 mm x 5 mm space on the reticle. Copy Right 2003 ELEN

27 Economics of Chip Making Cost per chip = (Chip Area / Wafer Area) X Cost per Wafer Yield to 80% to account for Streets Yield another 80% for test Yield Add package Cost Add test Cost Copy Right 2003 ELEN

28 Cost Analysis Example Chip Size: 1100 microns X 900 microns 4 inch wafer: Production cost is 3.0 k Cost per die = $3000 ( 1100 X 900/7,853,981,635) = $.37 Yield by 80% for streets: $.47 Electrical yield 80%: $.59 Add package cost (assume $.10 for a Plastic SOT89 Package): $.69 Add Testing cost (assume $.20): $.89 Copy Right 2003 ELEN

29 Technology Partitioning based on Performance by Application PA: HBT LNA: PHEMT Switch: PIN, or MESFET Mixer: HBT VCO: HBT Copy Right 2003 ELEN

30 Off Chip Component Choices Performance Reasons, Economic Reasons Large Inductors: Greater than 5 nh Large Capacitors: Greater than 20 pf No more than 60% of chip should be L or C (poor use of GaAs) High Q Inductors (PA s, LNA s, VCO s Requiring low loss inductors) Transformers, Hybrid Couplers, Baluns Precision Resistors, High Power Resistors Digital Circuits. Copy Right 2003 ELEN

31 Battery Choices in Wireless Communications Lithium Ion: 3.7 Volts per cell, up to 1700 mah Capacity in a Prismatic cell, 100 w-h/kg, 1000 cys Ni-MH: 1.2 Volts per cell, up to 1800 mah, Capacity in a AA size, 80 w-h/kg, 500 cys. Ni-CD: 1.2 Volts per cell, up to 1200 mah Capacity in a AA size, 60 w-h/kg, 1500 cys. Common Voltages available with a series of cells: 1.2 V, 2.4 V, 3.6 V, 4.8 V Discharge cycle reduces the available Voltage in the last 10% of a battery s life by about 20%. Copy Right 2003 ELEN

32 Battery Cell Voltage vs Discharge Percentage Copy Right 2003 ELEN

33 Why Handheld Equipment is Moving towards Lower Voltages Digital CMOS Power Dissipation = Standby power + Internal Dynamic Power + Output Dynamic Power = (Icc*Vcc) + ((Cpd + Cl) *Fclock* SQ Vcc): Dynamic Power decreases with Sq Vcc (1.0 V consumes ¼ power of 2.0 V) Reduce the number of Series Connected Cells. Problem: PA load line Resistance is Rl=SQ Vcc /2 Pout. Low Voltage means Low Rl, which is hard to match to 50 Ohms. For this reason, PA s are the most difficult devices to operated at low voltages. Copy Right 2003 ELEN

34 Test Fixtures RF Connectors (SMA female), Easy DC connections. Includes ALL off chip Components. Use PCBs (FR4 etc.) for Packaged Devices. Use Ceramic chip and wire Hybrids for bare chips. Design test fixtures for test cells. Copy Right 2003 ELEN

35 Package Options Plastic Metal / Ceramic BGA, PGA Package Parasitics are a major issue. Thermal issues Economics: When to test? What to test? Copy Right 2003 ELEN

36 Plastic Package (SOT89) with Typical Parasitic Elements Copy Right 2003 ELEN

37 Bottom Side of a BGA Package Copy Right 2003 ELEN

38 Recommended Test Equipment Network analyzer (Measure S parameters) Wafer Probe Station, and a set of RF probes Spectrum Analyzer Power meter Generators with Digital Modulation Power Supplies Copy Right 2003 ELEN