VLSI Design I; A. Milenkovic 1

Transcription

1 Course Administration CPE/EE 427, CPE 527 VLSI esign I 2: Sequtial Circuits epartmt of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milkovic ( Instructor: Aleksandar Milkovic milka@ece.uah.edu EB 217-L Mon. 5:30 PM 6:30 PM, W. 12:30 13:30 PM URL: TA: Joel Wilder Hws: Hw #3, #4 issued; ue 11/16/05 Projects: Prestations in class: 11/30/05 & 12/05/05 Lab emonstrations: 12/07/05 & 12/12/05 (3:55-5:15 Final project due: 12/14/07 (3:55 {exceptions 12/15/05 (3:00PM} Test II: 11/21/05 (esign for speed, design for power, circuit styles, sequtial logic 11/9/2005 VLSI esign I; A. Milkovic 2 Review: TG MUX Based Implemtation Review: MS ET Implemtation Master Slave! feedback (hold mode 11/9/2005 VLSI esign I; A. Milkovic 3! input sampled (transpart mode I 2 T 2 I 3 I 1 M T 1 T 3 master transpart slave hold! I 5 T 4 I 6 11/9/2005 VLSI esign I; A. Milkovic 4 I 4 master hold slave transpart Review: esign Review: Enable Buffered output + No backdriving X Enable: ignore wh = 0 Mux: increase latch - delay Clock Gating: increase setup time, skew Widely used in standard cells + Very robust (most important - Rather large - Rather slow (1.5 2 FO4 delays - High loading Symbol Multiplexer esign Clock Gating esign /9/2005 VLSI esign I; A. Milkovic 5 11/9/2005 VLSI esign I; A. Milkovic 6 VLSI esign I; A. Milkovic 1

2 Registers Review: Reset Force output low wh asserted Synchronous vs. asynchronous Symbol Synchronous Reset Asynchronous Reset Review: Set / Reset Set forces output high wh abled Flip-flop with asynchronous set and set set 11/9/2005 VLSI esign I; A. Milkovic 7 11/9/2005 VLSI esign I; A. Milkovic 8 Review: Sequcing logic output depds on currt inputs Sequtial logic output depds on currt and previous inputs Requires separating previous, currt, future Called state or toks Ex: FSM, pipeline in Finite Machine out 11/9/2005 VLSI esign I; A. Milkovic 9 Pipeline Sequcing Cont. If toks moved through pipeline at constant speed, no sequcing elemts would be necessary Ex: fiber-optic cable Light pulses (toks are st down cable Next pulse st before first reaches d of cable No need for hardware to separate pulses But dispersion sets min time betwe pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast toks so they don t catch slow ones. 11/9/2005 VLSI esign I; A. Milkovic 10 Sequcing Overhead Sequtial Use flip-flops to delay fast toks so they move through exactly one stage each cycle. Inevitably adds some delay to the slow toks Makes circuit slower than just the logic delay Called Some people call this ing overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequce Inputs Currt Outputs Next 11/9/2005 VLSI esign I; A. Milkovic 11 11/9/2005 VLSI esign I; A. Milkovic 12 VLSI esign I; A. Milkovic 2

3 Registers Timing Metrics System Timing Constraints In Out Inputs Outputs In t su data stable t c-q time time Currt Next T ( period Out output stable output stable time reg + logic T t c-q + t plogic + t su 11/9/2005 VLSI esign I; A. Milkovic 13 11/9/2005 VLSI esign I; A. Milkovic 14 Sequcing Elemts : Level ssitive a.k.a. transpart latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transpart Opaque Edge-trigger Sequcing Elemts : Level ssitive a.k.a. transpart latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transpart Opaque Edge-trigger (latch (latch (flop (flop 11/9/2005 VLSI esign I; A. Milkovic 15 11/9/2005 VLSI esign I; A. Milkovic 16 Sequcing Methods Timing iagrams Flip-flops 2-Phase es Pulsed es Flip-s Contamination and Propagation elays Prop. elay A Y A Y 2-Phase Transpart es Pulsed es 1 2 p t pw p /2 Half-Cycle 1 Half-Cycle 1 p q Cont. elay / Clk- Prop elay / Clk- Cont. elay - Prop elay - Cont. elay / Setup Time / Hold Time thold q q 11/9/2005 VLSI esign I; A. Milkovic 17 11/9/2005 VLSI esign I; A. Milkovic 18 VLSI esign I; A. Milkovic 3

4 Max-elay: Flip-s Max-elay: Flip-s tpd Tc ( ( setup tpd Tc t + tpcq /9/2005 VLSI esign I; A. Milkovic 19 11/9/2005 VLSI esign I; A. Milkovic 20 Min-elay: Flip-s Min-elay: Flip-s 1 t cd 1 t t t cd hold ccq /9/2005 VLSI esign I; A. Milkovic 21 11/9/2005 VLSI esign I; A. Milkovic 22 Max elay: 2-Phase es Max elay: 2-Phase es t = t + t Tc ( pd pd pd L3 3 ( 2 t = t + t Tc tpdq pd pd pd L q1 1 q q2 2 q /9/2005 VLSI esign I; A. Milkovic 23 11/9/2005 VLSI esign I; A. Milkovic 24 VLSI esign I; A. Milkovic 4

5 Min-elay: 2-Phase es Min-elay: 2-Phase es t t cd1, cd t t t t t cd cd ccq 1, 2 hold nonoverlap 1 1 Hold time reduced by nonoverlap 2 2 Hold time reduced by nonoverlap 2 2 Paradox: hold applies twice each cycle, vs. only once for flops Paradox: hold applies twice each cycle, vs. only once for flops But a flop is made of two latches! 2 But a flop is made of two latches! 2 11/9/2005 VLSI esign I; A. Milkovic 25 11/9/2005 VLSI esign I; A. Milkovic 26 Max elay: Pulsed es Max elay: Pulsed es tpd Tc max 144 ( p 1 1 p 2 2 ( setup tpd Tc max tpdq, tpcq + t tpw p 1 1 p q 1 q (a t pw > 1 (a t pw > p p (b t pw < t pw tpd tsetup t pw tpd tsetup (b t pw < 2 11/9/2005 VLSI esign I; A. Milkovic 27 11/9/2005 VLSI esign I; A. Milkovic 28 Min-elay: Pulsed es Min-elay: Pulsed es p tcd 1 t t t + t cd hold ccq pw p 1 Hold time increased by pulse width 2 p Hold time increased by pulse width 2 p p tpw p tpw /9/2005 VLSI esign I; A. Milkovic 29 11/9/2005 VLSI esign I; A. Milkovic 30 VLSI esign I; A. Milkovic 5

6 Time Borrowing In a flop-based system: ata launches on one rising edge Mus before next rising edge If it arrives late, system fails If it arrives early, time is wasted s have hard edges In a latch-based system ata can pass through latch while transpart Long cycle of logic can borrow time into next As long as each loop completes in one cycle (a (b 1 Time Borrowing Example Borrowing time across half-cycle boundary 2 Borrowing time across pipeline stage boundary Loops may borrow time internally but must complete within the cycle 11/9/2005 VLSI esign I; A. Milkovic 31 11/9/2005 VLSI esign I; A. Milkovic 32 How Much Borrowing? Clock Skew 2-Phase es t T c ( tsetup + t borrow nonoverlap borrow 2 Pulsed es t t t pw setup t 2 nonoverlap t /2 borrow Nominal Half-Cycle 1 elay 2 We have assumed zero skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing 11/9/2005 VLSI esign I; A. Milkovic 33 11/9/2005 VLSI esign I; A. Milkovic 34 Skew: Flip-s Skew: es cd hold ( setup skew tpd Tc tpcq + t + t t t t + t ccq skew t skew q 2 t skew 2-Phase es t Tc ( 2t pd pdq 123 t, t t t t + t cd cd ccq 1 2 hold nonoverlap skew t Tc ( tsetup 2 + t + tskew borrow nonoverlap Pulsed es t Tc max ( tpdq, tpcq + tsetup tpw + tskew pd L t t + t t + t cd hold pw ccq skew ( t t t + t borrow pw setup skew 11/9/2005 VLSI esign I; A. Milkovic 35 11/9/2005 VLSI esign I; A. Milkovic 36 VLSI esign I; A. Milkovic 6

7 Two-Phase Clocking If setup times are violated, reduce speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze skew An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times Call these s 1, 2 (ph1, ph2 Safe Flip- In class, use flip-flop with nonoverlapping s Very slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 2 X /9/2005 VLSI esign I; A. Milkovic 37 11/9/2005 VLSI esign I; A. Milkovic 38 Summary Flip-s: Very easy to use, supported by all tools 2-Phase Transpart es: Lots of skew tolerance and time borrowing Pulsed es: Fast, some skew tol & borrow, hold time risk 11/9/2005 VLSI esign I; A. Milkovic 39 VLSI esign I; A. Milkovic 7