Virtual Memory and Address Translation

Transcription

1 Virtual Memry and Address Translatin

2 Review! Prgram addresses are virtual addresses. Ø Relative ffset f prgram regins can nt change during prgram executin. E.g., heap can nt mve further frm cde. Ø Virtual addresses == physical address incnvenient. Prgram lcatin is cmpiled int the prgram.! A single ffset register allws the OS t place a prcess virtual address space anywhere in physical memry. Ø Virtual address space must be smaller than physical. Ø Prgram is swapped ut f ld lcatin and swapped int new.! Segmentatin creates external fragmentatin and requires large regins f cntiguus physical memry. Ø We lk t fixed sized units, memry pages, t slve the prblem. 2

3 Virtual Memry Cncept! Key prblem: Hw can ne supprt prgrams that require mre memry than is physically available? Ø Hw can we supprt prgrams that d nt use all f their memry at nce? 2 n -!! Hide physical size f memry frm users Ø Memry is a large virtual address space f 2 n bytes Ø Only prtins f VAS are in physical memry at any ne time (increase memry utilizatin).! Issues Ø Placement strategies Where t place prgrams in physical memry Ø Replacement strategies What t d when there exist mre prcesses than can fit in memry Ø Lad cntrl strategies Determining hw many prcesses can be in memry at ne time 0! Prgram P s VAS 3

4 Realizing Virtual Memry Paging (f MAX -, MAX -)!! Physical memry partitined int equal sized page frames Ø Page frames avid external fragmentatin. A memry address is a pair (f, ) f frame number (f max frames) frame ffset ( max bytes/frames) Physical address = max f + (f,)! Physical Memry PA: lg 2 (f max max ) lg 2 max f f (0,0)! 4

5 Physical Address Specificatins Frame/Offset pair v. An abslute index! Example: A 6-bit address space with ( max =) 52 byte page frames Ø Addressing lcatin (3, 6) =,542 (3,6)! PA: f Physical Memry,542!,542 (0,0)! 0! 5

6 Questins! The ffset is the same in a virtual address and a physical address. Ø A. True Ø B. False! If yur level data cache is equal t r smaller than 2 number f page ffset bits then address translatin is nt necessary fr indexing the data cache. Ø A. True Ø B. False 6

7 Realizing Virtual Memry Paging! A prcess s virtual address space is partitined int equal sized pages Ø page = page frame 2 n - =! (p MAX -, MAX -)! (p,)! A virtual address is a pair (p, ) p page number (p max pages) page ffset ( max bytes/pages) Virtual address = max p + p Virtual Address Space VA: lg 2 (p max max ) lg 2 MAX p (0,0)! 7

8 Paging Mapping virtual addresses t physical addresses Virtual Address Space! Pages map t frames! Pages are cntiguus in a VAS... Ø But pages are arbitrarily lcated in physical memry, and Ø Nt all pages mapped at all times (f, )! (p 2, 2 )! (p, )! Physical Memry (f 2, 2 )! 8

9 Frames and pages! Only mapping virtual pages that are in use des what? Ø A. Increases memry utilizatin. Ø B. Increases perfrmance fr user applicatins. Ø C. Allws an OS t run mre prgrams cncurrently. Ø D. Gives the OS freedm t mve virtual pages in the virtual address space.! Address translatin and changing address mappings are Ø A. Frequent and frequent Ø B. Frequent and infrequent Ø C. Infrequent and frequent Ø D. Infrequent and infrequent 9

10 Paging Virtual address translatin Prgram P! A page table maps virtual pages t physical frames (f,)! CPU P s Virtual Address Space (p,)! p Virtual Addresses f f Physical Addresses Physical Memry p Page Table 0

11 Virtual Address Translatin Details Page table structure table per prcess Part f prcess s state! Cntents: Ø Flags dirty bit, resident bit, clck/ reference bit Ø Frame number CPU p f PTBR + Virtual Addresses 0 0 f Physical Addresses p Page Table

12 Virtual Address Translatin Details Example A system with 6-bit addresses Ø 32 KB f physical memry Ø 024 byte pages (4,023)! P s Virtual Address Space (4,0)! (3,023)! 5 p CPU 0 9 Virtual Addresses 0 f Physical Addresses 0 Physical Memry Page Table (0,0)! 2

13 Virtual Address Translatin Perfrmance Issues! Prblem VM reference requires 2 memry references! Ø One access t get the page table entry Ø One access t get the data! Page table can be very large; a part f the page table can be n disk. Ø Fr a machine with 64-bit addresses and 024 byte pages, what is the size f a page table?! What t d? Ø Mst cmputing prblems are slved by sme frm f Caching Indirectin 3

14 Virtual Address Translatin Using TLBs t Speedup Address Translatin! Cache recently accessed page-t-frame translatins in a TLB Ø Fr TLB hit, physical page number btained in cycle Ø Fr TLB miss, translatin is updated in TLB Ø Has high hit rati (why?) CPU Physical Addresses f p Virtual Addresses? Key Value p f f TLB X! p Page Table 4

15 Dealing With Large Page Tables Multi-level paging! Add additinal levels f indirectin t the page table by sub-dividing page number int k parts Ø Create a tree f page tables Ø TLB still used, just nt shwn Ø The architecture determines the number f levels f page table Secnd-Level Page Tables Virtual Address p p 2 p 3 p 2 p 3 p First-Level Page Table Third-Level Page Tables 5

16 Dealing With Large Page Tables Multi-level paging! Example: Tw-level paging CPU Memry p p Virtual Addresses Physical Addresses f 6 0 PTBR + page table + f p p 2 First-Level Page Table Secnd-Level Page Table 6

17 The Prblem f Large Address Spaces! With large address spaces (64-bits) frward mapped page tables becme cumbersme. Ø E.g. 5 levels f tables.! Instead f making tables prprtinal t size f virtual address space, make them prprtinal t the size f physical address space. Ø Virtual address space is grwing faster than physical.! Use ne entry fr each physical page with a hash table Ø Translatin table ccupies a very small fractin f physical memry Ø Size f translatin table is independent f VM size! Page table has entry per virtual page! Hashed/Inverted page table has entry per physical frame 7

18 Virtual Address Translatin Using Page Registers (aka Hashed/Inverted Page Tables)! Each frame is assciated with a register cntaining Ø Residence bit: whether r nt the frame is ccupied Ø Occupier: page number f the page ccupying frame Ø Prtectin bits! Page registers: an example Ø Physical memry size: 6 MB Ø Page size: 4096 bytes Ø Number f frames: 4096 Ø Space used fr page registers (assuming 8 bytes/register): 32 Kbytes Ø Percentage verhead intrduced by page registers: 0.2% Ø Size f virtual memry: irrelevant 8

19 Page Registers Hw des a virtual address becme a physical address?! CPU generates virtual addresses, where is the physical page? Ø Hash the virtual address Ø Must deal with cnflicts! TLB caches recent translatins, s page lkup can take several steps Ø Hash the address Ø Check the tag f the entry Ø Pssibly rehash/traverse list f cnflicting entries! TLB is limited in size Ø Difficult t make large and accessible in a single cycle. Ø They cnsume a lt f pwer (27% f n-chip fr StrngARM) 9

20 Indexing Hashed Page Tables Using Hash Tables! Hash page numbers t find crrespnding frame number Ø Page frame number is nt explicitly stred ( frame per entry) Ø Prtectin, dirty, used, resident bits als in entry p 20 9 CPU Virtual Address PID running Physical Addresses f 6 9 Memry Hash =? =? tag check PTBR PID page + 0 f max f max 2 h(pid, p) Inverted Page Table 0 20

21 Searching Hahed Page Tables Using Hash Tables! Page registers are placed in an array! Page i is placed in slt f(i) where f is an agreed-upn hash functin! T lkup page i, perfrm the fllwing: Ø Cmpute f(i) and use it as an index int the table f page registers Ø Extract the crrespnding page register Ø Check if the register tag cntains i, if s, we have a hit Ø Otherwise, we have a miss 2

22 Searching Hashed Page Tables Using Hash Tables (Cnt d.)! Minr cmplicatin Ø Since the number f pages is usually larger than the number f slts in a hash table, tw r mre items may hash t the same lcatin! Tw different entries that map t same lcatin are said t cllide! Many standard techniques fr dealing with cllisins Ø Use a linked list f items that hash t a particular table entry Ø Rehash index until the key is fund r an empty table entry is reached (pen hashing) 22

23 Questins! Why use hashed/inverted page tables? Ø A. Frward mapped page tables are t slw. Ø B. Frward mapped page tables dn t scale t larger virtual address spaces. Ø C. Inverted pages tables have a simpler lkup algrithm, s the hardware that implements them is simpler. Ø D. Inverted page tables allw a virtual page t be anywhere in physical memry. 23

24 Virtual Memry (Paging) The bigger picture! A prcess s VAS is its cntext Ø Cntains its cde, data, and stack! Cde pages are stred in a user s file n disk Ø Sme are currently residing in memry; mst are nt! Data and stack pages are als stred in a file Ø Althugh this file is typically nt visible t users Ø File nly exists while a prgram is executing! OS determines which prtins f a prcess s VAS are mapped in memry at any ne time Cde Data Stack File System (Disk) OS/MMU Physical Memry 24

25 Virtual Memry Page fault handling Physical! Memry!! References t nn-mapped pages generate a page fault CPU Page fault handling steps: Prcessr runs the interrupt handler OS blcks the running prcess OS starts read f the unmapped page OS resumes/initiates sme ther prcess Read f page cmpletes OS maps the missing page int memry OS restart the faulting prcess 0 Page! Table! Prgram P s VAS Disk! 25

26 Virtual Memry Perfrmance Page fault handling analysis! T understand the verhead f paging, cmpute the effective memry access time (EAT) Ø EAT = memry access time prbability f a page hit + page fault service time prbability f a page fault! Example: Ø Memry access time: 60 ns Ø Disk access time: 25 ms Ø Let p = the prbability f a page fault Ø EAT = 60( p) + 25,000,000p! T realize an EAT within 5% f minimum, what is the largest value f p we can tlerate? 26

27 Virtual Memry Summary! Physical and virtual memry partitined int equal size units! Size f VAS unrelated t size f physical memry! Virtual pages are mapped t physical frames! Simple placement strategy! There is n external fragmentatin! Key t gd perfrmance is minimizing page faults 27

28 Segmentatin vs. Paging! Segmentatin has what advantages ver paging? Ø A. Fine-grained prtectin. Ø B. Easier t manage transfer f segments t/frm the disk. Ø C. Requires less hardware supprt Ø D. N external fragmentatin! Paging has what advantages ver segmentatin? Ø A. Fine-grained prtectin. Ø B. Easier t manage transfer f pages t/frm the disk. Ø C. Requires less hardware supprt. Ø D. N external fragmentatin. 28