UP49A. Quality Management ITM Semiconductor. Contents. Battery Protect Solution IC. 1. Features Page Outline Page Pin Assignment Page 3

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2 Conens 1. Feaures Page 1 2. Ouline Page 2 3. Pin Assignmen Page 3 4. Block Diagram Page 3 5. Absolue Maximum Raing Page 4 6. Elecrical Characerisics Page 4 7. Measuring Circui Page 9 8. Operaion Page 10 1) Overcharge deecor (D1) Page 10 2) Overdischarge deecor (D2) Page 10 3) Discharge overcurren deecor, Shor deecor (D3, Shor Deecor) Page 11 4) Charger overcurren deecor Page 11 5) Over volage charger deecor Page Applicaion Circui Page Timing Char Page Packing Spec Page Package Descripion Page Recommend Land Paern Page Marking Conens Page 20

3 Feaures 1.TheproecionICandTheDual-NchMOSFETousecommonDrainareinegraedino One-packaging IC. 2. Reduced Pin-Coun by fully connecing inernally. 3. Applicaion Par 1) Proecion IC 1 Uses high wihsand volage CMOS process. - The charger secion can be conneced up o absolue maximum raing Deecion volage precision - Overcharge deecion volage ±25m (Ta=25 ), ±45m (Ta=-30~70 ) - Overdischarge deecion volage ±100m (Ta=25 ), ±120m (Ta=-30~70 ) - Discharging overcurren deecion volage ±10m (Ta=25 ), ±20m (Ta=-30~70 ) - Charging overcurren deecion volage ±20m (Ta=25 ), ±40m (Ta=-30~70 ) 3 Buil-in deecion delay imes - Overcharge deecion delay ime 1.00±0.20s (Ta=25 ), 1.00[+0.50,-0.40]s (Ta=-30~70 ) - Overdischarge deecion delay ime) 96.0±19.2ms (Ta=25 ), 96.0[+48,-38.4] ms (Ta=-30~70 ) - Discharging overcurren deecion delay ime) 12.0±2.4ms (Ta=25 ), 12.0[+6,-4.8] ms (Ta=-30~70 ) - Charging overcurren deecion delay ime) 16.0±3.2ms (Ta=25 ), 16.0[+8.0,-6.4] ms (Ta=-30~70 ) - Shor deecion delay ime) 400[+160,-120] μs (Ta=25 ), 400[+400,-200] μs (Ta=-30~70 ) 4 Wih abnormal charger deecion funcion 5 0 charge funcion is no allowed 6 Auo Wake-up funcion is no allowed 2) FET 1 Using advanced rench echnology o provide excellen RDS(ON), low gae charge and operaion wih gae volage as low as 2.5 while reaining a 12 GS(MAX). 2 TheproecionforESD 3 Common drain configuraion 4 General characerisics -DS () = 20 -ID(A) = 3A -RSS(ON) <79mΩ (GS =4.5,ID =1A) - ESD Raing : 2000 HBM - 1 -

4 Ouline This is a baery proec soluion IC which is inegraed wih buil-in he proecion IC o use a lihium ion/lihium polymer secondary baeries developed for 1-cell series and Dual-Nch MOSFET. I funcions o proec he baery by deecing overcharge, overdischarge, discharge overcurren, charge overcurren and oher abnormaliies as urning off inernal Nch MOSFET. The proecion IC is composed of four volage deecors, shor deecion circui, reference volage sources, oscillaor, couner circui and logical circuis. The COUT pin (charge FET conrol pin) and DOUT pin (discharge FET conrol pin) oupus are CMOS oupu, and can drive he inernal Nch MOSFET direcly. The COUT oupu becomes low level afer delay ime fixed in he IC if overcharge is deeced. The DOUT oupu becomes low level afer delay ime fixed in he IC if overdischarge, discharge overcurren or shor is deeced. On overcharge sae, if he DD volage is less han he overcharge release volage, he COUT oupu becomes high level afer delay ime fixed in he IC. On overdischarge sae, if he volage of he baery rises more han he overdischarge deecion volage wih connecing he charger, he DOUT oupu becomes high level afer delay ime fixed in he IC. Charging curren canno be supplied o he baery lower han 0.9. Once discharge overcurren or shor have been deeced, if he sae of discharge overcurren or shor is released by opening he loads, he DOUT oupu becomes high level afer delay ime fixed in he IC. On overdischarge sae, he supply curren is reduced as less as possible. Once charge overcurren has been deeced, he sae of charge overcurren is released by opening he charger and seing he load

5 Pin Assignmen [ Package: UTEP-6L ] <Top view> N.C (No Connec ) 3 Source 2 4 Source 1(same as SS) <Boom view> N.C (No Connec ) 6 DD 7 Drain 8 N.C (No Connec ) Block Diagram Delay Shoren (No Used) Proecion IC DD D1 Overcharge D2 Oscillaor Overdischarge D3 Couner Charger Deecion D4 Logic Circui Delay Logic Circui Level Shif Shor TP - [N.C] Discharge Overcurren SS DOUT COUT Gae1 Gae2 Common Drain Dual-Nch MOSFET Source1 Source2 Drain - 3 -

6 Absolue Maximum Raing TOPR=25, Source1(SS)=0 Iem Symbol Raing Uni Supply olage DD -0.3 ~ 12 - Terminal Inpu olage - DD-28 ~ DD+0.3 DS Terminal Inpu olage DS SS-0.3 ~ DD+0.3 COUT Terminal Oupu olage COUT DD-28 ~ DD+0.3 DOUT Terminal Oupu olage DOUT SS-0.3 ~ DD+0.3 Operaion Temperaure TOPR -40 ~ +85 Sorage Temperaure TSTG -55 ~ +125 Drain-Source olage DS 20 Gae-Source olage GS ±12 Elecrical Characerisics Inpu olage Iem Symbol Measure Condiion Min. Typ. Max. Uni *1 Operaing Inpu olage DD1 DD - SS A Maximum forbidden volage for 0 charging Channel ON olage ST -= A COUT Pin Nch ON olage OL1 IOL=30 μa, DD= COUT Pin Pch ON olage OH1 IOH= -30 μa, DD= DOUT Pin Nch ON olage OL2 IOL=30 μa, DD= DOUT Pin Pch ON olage OH2 IOL= -30 μa, DD= Curren Consumpion Curren Consumpion IDD DD=3.9, -= μa L Curren Consumpion a Sand-By Over Charge olage Proecion Overcharge Deecion olage IS DD= μa L DET1 R1=1.0 kω TOPR= TOPR= -30~ B Overcharge Deecion Delay Time Overcharge Release olage Overcharge Release Delay Time DET1 DD= TOPR= s B TOPR= -30~ REL1 R1=1.0 kω TOPR= TOPR= -30~ REL1 DD= TOPR= ms B TOPR= -30~ B - 4 -

7 Iem Symbol Measure Condiion Min. Typ. Max. Uni *1 Over Discharge olage Proecion Overdischarge Deecion olage Overdischarge Deecion Delay Time Overdischarge Release olage 2 Overdischarge Release Delay Time DET2 -=0 R1=1.0 kω Noe : *1 The es circui symbols. *2 The parameer is guaraneed by design. TOPR= TOPR= -30~ DET2 DD= TOPR= ms D TOPR= -30~ REL2' REL2 Discharge Overcurren Proecion Discharging Overcurren Deecion olage Discharging Overcurren Deecion Delay Time Discharging Overcurren Deecion Curren Discharging Overcurren Release Delay Time DET3 DET3 IDET3 REL3 Charge Overcurren Proecion Charging Overcurren Deecion olage Charging Overcurren Deecion Delay Time Charging Overcurren Deecion Curren Charging Overcurren Release Delay Time Shor Proecion DET4 DET4 IDET4 REL4 chg = 4.2 R1=1.0 kω R2=2.2 kω DD= =-0.5 DD=3.2 R2=2.2 kω DD=3.2 -=0 0.2 DD=3.9 R2=2.2 kω DD=3.2 -=3.2 0 DD=3.5 R2=2.2 kω DD=3.5 -=0-1 DD=3.9 R2=2.2 kω DD=3.5 -=-1 0 Shor Deecion olage SHORT DD=3.2 Shor Deecion Delay Time Rese Resisance Overcurren Release Resisance SHORT DD=3.2 -=0 3.2 TOPR= TOPR= -30~ TOPR= TOPR= -30~ TOPR= TOPR= -30~ TOPR= TOPR= -30~ TOPR= A - TOPR= TOPR= -30~ TOPR= TOPR= -30~ TOPR= TOPR= -30~ TOPR= A - TOPR= TOPR= -30~ TOPR= TOPR= -30~ TOPR= TOPR= -30~ RSHORT DD=3.6, -= kω F Over olage Charger Proecion Over olage Charger chg1 DD=3.6, R2=2.2kΩ A Deecion olage Over olage Charger Release olage chg2 DD=3.6, R2=2.2 kω A ms ms ms ms ms μs D D E F F F G G G F F - 5 -

8 Iem Symbol Measure Condiion Min. Typ. Max. Uni *1 Inegraed MOSFET Drain-Source Breakdown olage BDSS ID=250 μa, GS= Zero Gae olage Drain Curren IDSS DS=16, GS= TJ= μa Gae-Body Leakage Curren Gae-Source Breakdown olage IGSS DS=0, GS=± μa BGSO DS=0, IG=±250 μa ± Gae Threshold olage GS(h) DS=GS, ID=250 μa Saic Source-Source ON-Resisance RSS(ON) GS=10, ID=5A TJ= mω GS=4.5, ID=1A mω GS=3.9, ID=1A mω GS=3.5, ID=1A mω GS=3.0, ID=1A mω GS=2.5, ID=1A mω Diode Forward olage SD IS=1A, GS= Maximum Body-Diode Coninuous Curren IS A - 6 -

9 GS = 10 I D = 1 A GS = 4.5 I D = 1 A GS =2.5 GS = GS = 2.5 I D = 1 A GS =

10 80 70 I D = 5A

11 Measuring Circui A. E. DD - Source1 (SS) TP or Nc Nc Source2 DD - Source1 (SS) TP or Nc Nc Source2 B. F. DD TP or Nc DD TP or Nc - Source1 (SS) Nc Source2 A - Source1 (SS) Nc Source2 C. G. DD TP or Nc DD TP or Nc - Source1 (SS) Nc Source2 - Source1 (SS) Nc Source2 D. H. DD - Source1 (SS) TP or Nc Nc Source2 A DD - Source1 (SS) TP or Nc Nc Source2-9 -

12 Operaion 1. Overcharge deecor (D1) The D1 moniors DD pin volage during charge. In he sae of charging he baery, i will deec he overcharge sae of he baery if he DD erminal volage becomes higher han he overcharge deecion volage(typ ). And hen he COUT erminal urns o low level, so he inernal charging conrol Nch MOSFET urns OFF and i forbids o charge he baery. Afer deecing overcharge, i will release he overcharge sae if he DD erminal volage becomes lower han he overcharge release volage(typ.4.025). And hen he COUT erminal urns o high level, so he inernal charging conrol Nch MOSFET urns ON, and i acceps o charge he baery. When he DD erminal volage is higher han he overcharge deecion volage, o disconnec he charger and connec he load, leave he COUT erminal low level, bu i acceps o conduc load curren via he paraciical body diode of he inernal Nch MOSFET. And hen if he DD erminal volage becomes lower han he overcharge deecion volage, he COUT erminal urns o high level, so he inernal Nch MOSFET urn ON, and i acceps o charge he baery. The overcharge deecion and release have delay ime decided inernally. When he DD erminal volage becomes higher han he overcharge deecion volage, if he DD erminal volage becomes lower han he overcharge deecion volage again wihin he overcharge deecion delay ime(typ. 1.00s), i will no deec overcharge. And in he sae of overcharge, when he DD erminal volage becomes lower han he overcharge release volage, if he DD erminal volage backs higher han he overcharge release volage again wihin he overcharge release delay ime(typ. 2.0ms), i will no release overcharge. The oupu driver sage of he COUT erminal includes a level shifer, so i will oupu he - erminal volage as low level.the oupuypeofhecout erminal is CMOS oupu beween DD and - erminal volage. 2. Overdischarge deecor (D2) The D2 moniors DD pin volage during discharge. In he sae of discharging he baery, i will deec he overdischarge sae of he baery if he DD erminal becomes lower han he overdischarge deecion volage (Typ ). And hen he DOUT erminal urns o low level, so he inernal discharging conrol Nch MOSFET urn OFF and i forbids o discharge he baery. The release from he overdiscahrge sae is done by connecing he charger. If he charger is conneced and he DD erminal volage is lower han he overdischarge deecion volage, i acceps o conduc charge curren via he paraciical body diode of he inernal Nch MOSFET. And hen if he DD erminal volage becomes higher han he overdischarge deecion volage, he DOUT erminal urns o high level, so he inernal Nch MOSFET urns ON, and i acceps o discharge he baery. If he charger is conneced and he DD erminal volage is higher han he overdiscahrge deecion volage, he DOUT erminal will urn o high level wih he delay ime

13 Charging curren canno be supplied o he baery ha is discharged o lower han he maximum forbidden volage (Typ 0.9) for 0 charging. The overdischarge deecion have delay ime decided inernally. When he DD erminal volage becomes lower han he overdischarge deecion volage, if he DD erminal volage becomes higher han he overdischarge deecion volage again wihin he overdischarge deecion delay ime (Typ. 96.0ms), i will no deec overdischarge. Moreover, he overdischarge release delay ime (Typ. 4.0ms) exiss, oo. All he circuis are sopped, and afer he overdischarge is deeced, i is assumed he sae of he sandby, and decreases he curren (sandby curren) which IC consumes as much as possible. (When DD=2, Max. 0.1uA). The oupu ype of he DOUT erminal is CMOS oupu beween DD and SS erminal volage. 3. Discharge overcurren deecor, Shor deecor (D3, Shor Deecor) In he sae of chargable and dischargabe, D3 moniors he volage level of - pin. If he - erminal volage becomes higher han he discharging overcurren deecion volage (Typ ) by shor of loads, ec., i will deec discharging overcurren sae. If he - erminal volage becomes higher hen shor deecion volage (Typ. 0.9), i will deec discharging overcurren sae, oo. And hen he DOUT erminal oupus low level, so he inernal discharging conrol Nch MOSFET urns OFF, and i proecs from large curren discharging. The discharging overcurren deecion has delay ime decided inernally. When he - erminal volage becomes higher han he discharging overcurren deecion volage, if he - erminal volage becomes lower han he discharging overcurren deecion volage wihin he discharging overcurren deecion delay ime (Typ. 12ms), i will no deec discharging overcurren. Morever, he discharging overcurren release delay ime (Typ. 4.0ms) exiss, oo. The shor deecion delay ime (Typ. 400us) decided inernally exiss, oo. The discharging overcurren release resisance (Typ. 50kohm) is buil ino beween - erminal and SS erminal. In he sae of discharging overcurren or shor, if he load is opened, - erminal is pulled down o he SS via he discharging overcurren release resisance. Andwhenhe- erminal volage becomes lower han he discharging overcurren deecion volage, i will auomaically release discahrging overcurren or shor sae. if discharging overcurren or shor is deeced, he discharging overcurren release resisance urns ON. On he normal sae (chargable and dischargable sae), he discharging overcurren release resisance is OFF. 4. Charge overcurren deecor (D4) In he sae of chargable and dischargable, D4 moniors he volage level of - pin. If he - erminal volage becomes lower han charging overcurren deecion volage (Typ ) by abnormal volage or curren charger, ec., i will deec charging overcurren sae. And hen he COUT erminal oupus low level, so he inernal charging conrol Nch MOSFET urn OFF, and i proecs from large curren charging

14 I release charging overcurren sae if he abnormal charger is disconneced and he load is conneced. The charging overcurren deecion has delay ime decided inernally. When he - erminal volage becomes lower han he charging overcurren deecion volage, if he - erminal volage becomes higher han he charging overcurren deecion volage wihin he charging overcurren deecion delay ime (Typ. 16.0ms), i will no deec charging overcurren. Morever, he charging overcurren release delay ime (Typ. 4.0ms) exiss, oo. 5. Over volage charger deecor By monioring charger volage beween DD erminal and - erminal, and when he volage becomes higher han over volage charger deecion volage (Typ.8.0), COUT oupu becomes low level and inernal Nch MOSFET is urned o OFF. And when he volage becomes lower han over volage charger release volage (Typ.7.3), COUT oupu becomes high level and inernal Nch MOSFET is urned o ON. Please noe ha he larger value of R2, he larger deecion volage. There is no delay ime of deecion and release for his funcion

15 Applicaion Circui (Example) + P+ R1 1.0 kω Delay Shoren (No Used) Proecion IC TP DD D1 Overcharge D2 Oscillaor Overdischarge Charger Deecion D4 D3 Couner Logic Circui Delay Logic Circui Level Shif Shor - C2 0.1 μf C1 0.1 μf Discharge Overcurren SS DOUT COUT Gae1 Gae2 Common Drain Dual-Nch MOSFET R2 2.2 kω Source1 Source2 - P- Drain C3 0.1 μf Applicaion Hin R1 and C1 sabilize a supply volage ripple. However, he deecion volage rises by he curren of peneraion in IC of he volage deecion when R1 is enlarged, so he value of R1 is adjused o 1kohm or less. Moreover, adjus he value of C1 o 0.01uF or more o do he sabiliy operaion, please. R1 and R2 resisors are curren limi resisance if a charger is conneced reversibly or a highvolage charger ha exceeds he absolue maximum raing is conneced. R1 and R2 may cause a power consumpion will be over raing of power dissipaion, herefore he `R1+R2` should be more han 1kohm. Moreover, if R2 is oo enlarged, he charger connecion release canno be occasionally done afer he overdischarge is deeced, so adjus he value of R2 o 10kohm or less, please. C2 and C3 capaciors have effec ha he sysem sabiliy abou volage ripple or impored noise. Afer check characerisics, decide ha hese capaciors should be insered or no, where should be insered, and capaciance value, please

16 Timing Char 1. Overcharge, Charging overcurren operaions Connec Charger Connec Load Connec Charger Connec Load Overcurren Charger Open Charger, Connec Load DD DET1 REL1 - DD DET3 SS DET4 COUT DET1 DET1 DET4 DD REL1 REL1 REL4 - ICHARGE 0 IDISCHARGE

17 2. Overcharge, Overvolage charger operaions Connec Charger Connec Load Connec Charger Connec Load Open Load Connec Over olage Charger Open Charger DD DET1 REL1 - DD DET3 SS COUT DET1 DET1 DD REL1 REL1 - ICHARGE 0 IDISCHARGE

18 3. Overdischarge, Discharging Overcurren and Shor operaions Overcurren DD Connec Load Connec Charger Connec Load Connec Charger Open Shor Open DET2 - DD SHORT DET3 SS DOUT DET2 DET2 DET3 SHORT DD REL2 REL2 REL3 REL3 - ICHARGE 0 IDISCHARGE

19 Packing spec Carrier ape spec Reelspec LABEL REEL LABEL Tapingspec

20 OUTER BOX PACKING SPECIFICATION OUT BOX LABEL Ani-saic bag packing Tape Reel Inner box Ou box

21 Package Descripion [ETCHED Type] [STAMP Type] NOTE Recommend Land Paern (imeshare) (1) Pin (1) Pin [mm]

22 Marking Conens Indicae 1's Pin Model No. AYWLT Lo serial No. Dae code Producing sie