Paper Entered: December 22, 2014 UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD

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1 Paper Entered: December 22, 2014 UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD SPANSION INC., SPANSION LLC, and SPANSION (THAILAND) LTD., Petitioner, v. MACRONIX INTERNATIONAL CO., LTD., Patent Owner. Case IPR Before KRISTEN L. DROESCH, KALYAN K. DESHPANDE, and GRACE KARAFFA OBERMANN, Administrative Patent Judges. DROESCH, Administrative Patent Judge. DECISION Denying Institution of Inter Partes Review 37 C.F.R

2 I. INTRODUCTION A. Background Spansion Inc., Spansion LLC, and Spansion (Thailand) Ltd. (collectively Petitioner ) filed a Petition (Paper 5, Petition or Pet. ) to institute inter partes review of claims 1 8 ( the challenged claims ) of U.S. Patent No. 6,552,360 B1 (Ex. 1001, the 360 Patent ). See 35 U.S.C Macronix International Co., Ltd. ( Patent Owner ) filed a Preliminary Response ( Prelim. Resp. ). Paper 11. An inter partes review may be authorized only if the information presented in the petition... and any [preliminary] response... shows that there is a reasonable likelihood that the petitioner would prevail with respect to at least 1 of the claims challenged in the petition. 35 U.S.C. 314(a). Because Petitioner fails to meet that burden, we decline to institute review. B. Related Proceeding Petitioner and Patent Owner indicate the 360 Patent is at issue in Certain Non-Volatile Memory Devices and Products Containing Same, USITC Inv. No. 337-TA-909 ( the ITC 909 Investigation ). Pet. 8; Paper 10, 2. C. The 360 Patent (Ex. 1001) The 360 Patent relates to a circuit layout on a substrate of a semiconductor wafer that is suitable for reducing defects during a chemical mechanical polishing (CMP) process. Ex. 1001, Abs.; col. 2, ll During the CMP process, mechanical pressure of the polishing head is exerted on the wafer s surface, and a chemical reaction of the polishing slurry reacts on the wafer s surface. Id. at col. 1, ll Parameters having influence on the CMP process include: the polishing pressure 2

3 exerted by polishing heads and topography of wafers, rotation speeds of wafers and polishing heads, composition of polishing particles and polishing slurry[,] and the material of the polishing pad and its abrasion hardness, and so forth. Id. at col. 1, ll Figure 4 of the 360 Patent is reproduced below: Figure 4 illustrates boundary 150 between active layers of the wafer, diffusion regions 140, a plurality of strips of first circuit structure 130a, and two strips of second circuit structure 130b linking the front ends and rear ends of the plurality of strips of first circuit structure 130a. Ex. 1001; col. 4, ll ; col. 4, l. 59 col. 5, l. 12. Due to the first circuit structure 130a ha[ving] the same dielectric and conductive layers [as] the second circuit structure 130b, the structure strength or the rigidity of both front and rear ends of the first circuit structure 130a can be effectively enhanced, and thus the polishing pressure can be sufficiently averaged in the CMP process, as arrows shown in Fig. 4. Id. at col. 4, ll D. Illustrative Claim Claim 1, reproduced below, is illustrative of the claims at issue: 1. A circuit layout on a substrate of a semiconductor wafer, suitable for reducing defects during a chemical mechanical 3

4 polishing process, said substrate comprising a plurality of strips of first circuit structure, said circuit layout comprising: at least two strips of second circuit structure located on said substrate of said semiconductor wafer, each of said two strips of second circuit structure respectively linking the front end and the rear end of said plurality of strips of said first circuit structure, utilizing to average polishing pressure performed upon the front end and the rear end of said plurality of strips of said first circuit structure during said chemical mechanical polishing process for reducing defects occurred. E. Asserted Grounds of Unpatentability Petitioner contends the challenged claims are unpatentable under 35 U.S.C. 102/103 on the following specific grounds (Pet. 8 9): Claim(s) Basis Reference(s) Yama and Evans Yama, Evans, and the knowledge of a person of ordinary skill in the art Yama, Evans, and Fulford 1 4 and Yama and Lehr Yama, Lehr, and the knowledge of a person of ordinary skill in the art Yama, Lehr, and Fulford 1, 6 2, and Lehr Lehr and knowledge of person of ordinary skill in the art 1 4 and Lehr and Yama 1 The Petition relies on the following references: U.S. Patent No. 6,121,657 (Ex. 1003) ( Yama ); U.S. Patent No. 5,907,762 (Ex. 1004) ( Evans ); U.S. Patent No. 5,918,126 (Ex. 1008) ( Fulford ); and U.S. Patent No. 6,559,547 B1 (Ex. 1005) ( Lehr ). The Petition also relies on the Declaration of Dr. Peter S. Gwozdz (Ex. 1014). 2 The Petition omits claim 6 on page 9, but includes claim 6 as anticipated by Lehr on page 43. Compare Pet. 9, with Pet

5 A. Claim Construction II. ANALYSIS We interpret claims in an unexpired patent using the broadest reasonable interpretation in light of the specification. See 37 C.F.R (b); Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012). Petitioner contends the broadest reasonable interpretation must include Patent Owner s constructions from the ITC 909 Investigation for the following claim terms or phrases: circuit layout, circuit structure, located on, wherein said first circuit structure is located on an active region of said semiconductor wafer, wherein said substrate and said semiconductor wafer among said first circuit structure are diffusion regions, said active regions, width of said second circuit structure is about 0.3 m, and wherein said first circuit structure and said second circuit structure comprises a conductive layer and an insulating layer, located upon said conductive layer. Pet Patent Owner agrees explicitly with Petitioner s contentions. Prelim. Resp In addition, Patent Owner asserts the first circuit structure should be construed consistent with the construction for circuit structure i.e., first portion of an active device. Id. at 6. For purposes of our decision, no explicit constructions are necessary for the aforementioned claim terms and phrases. Petitioner also asserts the broadest reasonable interpretation of, at least two strips of second circuit structure located on said substrate of said semiconductor wafer, each of said two strips of second circuit structure respectively linking the front end and the rear end of said plurality of strips of said first circuit structure, utilizing to average polishing pressure performed upon the front end and the rear end of said plurality of strips of 5

6 said first circuit structure during said chemical mechanical polishing process for reducing defects occurred, must include Patent Owner s following construction from the ITC 909 Investigation: a strip of the second circuit structure connecting all of the front ends of the two or more strips of the first circuit structure and another strip of the second circuit structure connecting all of the rear ends of the same two or more strips of the first circuit structure used in a chemical mechanical polishing process. Pet Patent Owner agrees explicitly with Petitioner s assertion. Prelim. Resp. 6. However, Petitioner and Patent Owner do not explain why omission of the claim phrase utilizing to average polishing pressure performed upon the front end and the rear end of said plurality of strips of said first circuit structure during said chemical mechanical polishing process for reducing defects occurred is reasonable, and comports with the broadest reasonable interpretation. See Pet ; Prelim. Resp. 6. The claim phrase utilizing to average polishing pressure performed upon the front end and the rear end of said plurality of strips of said first circuit structure during said chemical mechanical polishing process is functional language 3. This language describes the second circuit structure as functioning to average the polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during a CMP process. We are not persuaded that the agreed-upon construction, omitting this functional language, is reasonable. It is permissible to recite 3 Patent Owner also considers implicitly this language to be functional language. See Prelim. Resp. 21 ( the structure(s) that Petitioners identify as the second circuit structure cannot function to average the polishing pressure on the front and rear ends of the first circuit structures during CMP ). 6

7 features of an apparatus either structurally or functionally. In re Schreiber, 128 F.3d 1473, 1478 (Fed. Cir. 1997) (citing In re Swinehart, 439 F.2d 210, (CCPA 1971)). In some circumstances, functional language can be used to add limitations to an apparatus claim. See K-2 Corp. v. Salomon S.A., 191 F.3d 1356, 1363 (Fed. Cir. 1999). However, functional language may not be given patentable weight if the prior art discloses, teaches, or suggests a structure that inherently possesses the functionally defined limitations that is, a structure capable of performing the function. See Schreiber, 128 F.3d at ; see also Swinehart, 439 F.2d at ( it is elementary that the mere recitation of a newly discovered function or property inherently possessed by things in the prior art, does not cause a claim drawn to those things to distinguish over the prior art ). B. Grounds of Unpatentability Based on Lehr as the Primary Reference Petitioner presents the following contentions: (1) claims 1, 6, and 7 are unpatentable under 35 U.S.C. 102(e) as anticipated by Lehr; (2) claims 1 8 are unpatentable under 35 U.S.C. 103(a) as obvious over Lehr and the knowledge of a person of ordinary skill in the art; and (3) claims 1 4 and 8 are unpatentable under 35 U.S.C. 103(a) as obvious over Lehr and Yama. Pet. 8 9, Lehr (Ex. 1005) Lehr discloses a semiconductor structure including a patterned metallization layer having a contact area formed of a plurality of contiguous individual structures, a dielectric layer covering the metallization area, and the individual structures forming a grating of mutually parallel line 7

8 structures, or a network of intersecting line structures. Ex. 1005, col. 4, ll ; claims 1, 4, 5. Figures 4A and 4B of Yama are reproduced below: Figure 4A shows grating of parallel line structures 4 surrounded by frame 6. Ex. 1005, col. 4, ll Figure 4B shows network of intersecting line structures 4 surrounded by frame 6. Id. 2. Anticipation of Claims 1, 6, and 7 by Lehr Petitioner asserts that Lehr discloses [a] circuit layout on a substrate of a semiconductor wafer... comprising a plurality of strips of first circuit structure, based on Lehr s depiction of the grating of parallel line structures 4 in Figures 4A and 4B. Pet (citing Ex. 1005, col. 1, ll ; col. 3, ll. 6 18, 53 54; col. 4, ll ; Figs. 2, 4A, 4B; Ex , app. D 65 66). Petitioner further asserts that Lehr discloses at least two strips of second circuit structure located on said substrate of said semiconductor wafer, each of said two strips of second circuit structure respectively linking the front end and the rear end of said plurality of strips of said first circuit structure, based on the horizontal portions of Lehr s frame 6 depicted in Figures 4A and 4B. Id. at (citing Ex. 1005, col. 1, ll ; col. 1, l. 8

9 66 col. 2, l. 5; col. 3, ll ; col. 4, ll ; Figs. 4A, 4B; Ex , app. D 66 68). Petitioner does not address sufficiently the functional language, discussed above in Section II.A., describing the second circuit structure as functioning to average the polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during a CMP process. At best, Petitioner presents an argument in a footnote, asserting that a person of ordinary skill in the art would have understood that the grid arrangement in Lehr, upon applying pressure during CMP, would inherently be utilized to average polishing pressure as claimed, because polishing during CMP would necessarily apply an average polishing pressure across the grid arrangement. Pet. 45 n.23 (citing Ex , app. D 66 68). We are not persuaded by Petitioner s inherency assertion because it is not supported by a sufficient factual basis. See Pet. 45 n.23 (citing Ex , app. D 66 68); Ex ; see also Prelim. Resp. 33 ( Petitioners and their expert, in a conclusory fashion, assert that Lehr s structure would inherently average the polishing pressure ). Specifically, Petitioner does not provide objective evidence sufficient to support a finding that polishing during CMP would apply necessarily an average polishing pressure across Lehr s grid arrangement. As discussed in the 360 Patent Specification, parameters having influence on the CMP process include: the polishing pressure exerted by polishing heads and topography of wafers, rotation speeds of wafers and polishing heads, composition of polishing particles and polishing slurry[,] and the material of the polishing pad and its abrasion hardness, and so forth. Ex. 1001, col. 1, ll For example, instead of 9

10 addressing any of the influential parameters of the CMP process (e.g., topography of wafers), paragraph 40 of the Declaration merely explains Dr. Gwozdz s understanding of an obviousness analysis under 35 U.S.C Ex Similarly, pages of Appendix D of Dr. Gwozdz s Declaration include a claim chart and footnotes that are identical substantially to the claim chart and footnotes presented in the Petition. Compare Ex app. D 65 68, with Pet ; compare Ex app. D 68 n.11, with Pet. 45 n.23. In other words, the relevant portions of Dr. Gwozdz s Declaration consist of bare opinion, without objective support. See 37 C.F.R (a) ( testimony that does not disclose the underlying facts or data on which the opinion is based is entitled to little or no weight ). The information presented in the Petition, therefore, is insufficient to support a finding of inherency. Therefore, based on the record before us, we determine there is not a reasonable likelihood that Petitioner would prevail on its assertion that claim 1, and dependent claims 6 and 7, are anticipated by Lehr. 3. Obviousness of Claims 1 8 Over Lehr and the Knowledge of a Person of Ordinary Skill in the Art, and Obviousness of Claims 1 4 and 8 Over Lehr and Yama As applied by Petitioner, the knowledge of a person of ordinary skill in the art, and the teachings of Yama, do not remedy the deficiencies of Lehr addressed above with respect to claim 1. See Pet Accordingly, there is not a reasonable likelihood that Petitioner would prevail on its assertions that claims 1 8 would have been obvious over Lehr and the knowledge of a person of ordinary skill in the art, and that claims 1 4 and 8 would have been obvious over Lehr and Yama. 10

11 C. Grounds of Unpatentability Based on Yama and Lehr as the Primary References Petitioner presents the following contentions: (1) claims 1 4 and 6 8 are unpatentable under 35 U.S.C. 103(a) as obvious over Yama and Lehr; (2) claim 5 is unpatentable under 35 U.S.C. 103(a) as obvious over Yama, Lehr, and the knowledge of a person of ordinary skill in the art; and (3) claim 6 is unpatentable under 35 U.S.C. 103(a) as obvious over Yama, Lehr, and Fulford. Pet. 8 9, 24 42, Yama (Ex. 1003) Yama describes a layout of a conventional metal oxide semiconductor (MOS) transistor. Ex. 1003, col. 3, l. 19; Fig. 3. Figure 3 of Yama is reproduced below: Figure 3 illustrates MOS transistor T1 including a diffusion region that becomes source region 1a and drain region 1b, gate 2, metal interconnection layers 3a, 3b, connection hole (contact) 4, and metal interconnection layer 3c outside the diffusion region. Ex. 1003, col. 1, ll , 61 64; col. 2, ll Gate 2 is formed of a plurality of parallel lines of polysilicon provided above the region between source region 1a and drain region 1b. Id. at col. 1, ll The plurality of source regions 1a and drain regions 1b 11

12 are respectively connected by metal interconnections layers 3a, 3b, to function as one source electrode and one drain electrode. Id. at col. 1, ll Each diffusion region and each metal interconnection layer are connected by a connection hole (contact) 4. Id. at col. 1, l. 66 col. 2, l. 1. Gate 2 is connected by metal interconnection layer 3c outside the diffusion region. Id. at col. 2, ll Obviousness of Claims 1 4 and 6 8 Over Yama and Lehr Petitioner asserts that Yama teaches [a] circuit layout on a substrate of a semiconductor wafer... comprising a plurality of strips of first circuit structure, based on Yama s MOS transistor T1 depicted in Figure 3, including certain horizontal portions of the plurality of parallel lines of polysilicon gate 2. Pet (citing Ex. 1003, col. 1, ll ; Fig. 3; Ex , app. D 49 50). Petitioner further asserts that Yama teaches at least two strips of second circuit structure located on said substrate of said semiconductor wafer, each of said two strips of second circuit structure respectively linking the front end and the rear end of said plurality of strips of said first circuit structure, based on Yama s MOS transistor T1 depicted in Figure 3 including metal interconnection layer 3c and vertical portions of polysilicon gate 2 linking the front and rear ends of the horizontal portions of the parallel lines of polysilicon gate 2. Id. at (citing Ex. 1003, col. 2, ll. 1 10; col. 3, ll ; Fig. 3; Ex , app. D 50 52). Petitioner also relies on horizontal portions of Lehr s frame 6 depicted in Figures 4A and 4B for teaching at least two strips of second circuit structure located on said substrate of said semiconductor wafer, each of said two strips of second circuit structure respectively linking the front end and the rear end of said plurality of strips of said first circuit 12

13 structure, utilizing to average polishing pressure performed upon the front end and the rear end of said plurality of strips of said first circuit structure during said chemical mechanical polishing process for reducing defects occurred. Id. at (citing Ex. 1005, col. 1, ll ; col. 3, ll. 6 24, 53 54; col. 4, ll ; Figs. 4A, 4B; Ex , 60 61, app. D 52 55). Petitioner contends that it would have been obvious to a person of ordinary skill in the art to combine Yama s teachings of a MOS transistor with Lehr s teachings regarding the benefits of including improved planarization, reduction in CMP defects, and improved device yield, resulting from Lehr s grid-shaped structure. Pet (citing Ex ). In support of its contention of obviousness, Petitioner presents the following assertions: (1) Yama discloses a polysilicon layer having the same layout as the grid arrangement in Lehr (citing Ex. 1003, Fig. 3; Ex. 1005, Fig. 4A; Ex ); (2) Lehr teaches the grid arrangement can be fabricated to improve the deposition of dielectric layers and, thereby, reduce defects causing faults that persist after CMP (citing Ex. 1005, Abs.); and (3) a person of ordinary skill in the art would understand that planarizing the dielectric layer using CMP would improve device yield (citing Ex ). Id. On this record, there is not a reasonable likelihood that the combination of Yama and Lehr teaches or suggests the claimed invention. Petitioner does not address sufficiently the functional language, addressed above in Section II.A., describing the second circuit structure as functioning to average the polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during a CMP process. For example, Petitioner does not explain sufficiently how Yama s 13

14 metal interconnection layer 3c and vertical portions of polysilicon gate 2 depicted in Figure 2 (i.e., second circuit structure), as modified by the teachings of Lehr, inherently possesses the functionally-defined limitations that is, a structure capable of averaging the polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during a CMP process. Accordingly, based on the record before us, we determine there is not a reasonable likelihood that Petitioner would prevail on its assertion that claim 1, and dependent claims 2 4 and 6 8, would have been obvious over Yama and Lehr. 3. Obviousness of Claim 5 Over Yama, Lehr, and the Knowledge of a Person of Ordinary Skill in the Art, and Obviousness of Claim 6 Over Yama, Lehr, and Fulford As applied by Petitioner, the knowledge of a person of ordinary skill in the art, and the teachings of Fulford, do not remedy the deficiencies of the combined teachings of Yama and Lehr addressed above with respect to claim 1. See Pet , Therefore, there is not a reasonable likelihood that Petitioner would prevail on its assertions that claim 5 would have been obvious over Yama, Lehr, and the knowledge of a person of ordinary skill in the art, and that claim 6 would have been obvious over Yama, Lehr, and Fulford. D. Grounds of Unpatentability Based on Yama and Evans as the Primary References Petitioner presents the following contentions: (1) claims 1 8 are unpatentable under 35 U.S.C. 103(a) as obvious over Yama and Evans; (2) claim 5 is unpatentable under 35 U.S.C. 103(a) as obvious over Yama, Evans, and the knowledge of a person of ordinary skill in the art; and (3) 14

15 claim 6 is unpatentable under 35 U.S.C. 103(a) as obvious over Yama, Evans, and Fulford. Pet. 8 9, 24 42, Evans (Ex. 1004) Evans discloses a method of constructing a single-transistor ferroelectric memory (FEM) cell including chemically-mechanically polishing the constituent parts. Ex. 1004; Abs.; col. 1, l. 66 col. 2, l. 14. Evans discloses that using conventional manufacturing methods of etching and polishing, problems may arise due to short circuits caused by residual metal particles from the conductive electrodes of the capacitor contaminating the ferroelectric (FE) material and the surrounding oxides. Id. at col. 1, ll One object of Evan s invention is to manufacture a FEM cell that is not susceptible to short circuiting by residual metal particles. Id. at col. 2, ll Obviousness of Claims 1 8 Over Yama and Evans Petitioner relies on Yama, as discussed above in Section II.C.2., for teaching [a] circuit layout on a substrate of a semiconductor wafer... comprising a plurality of strips of first circuit structure, and at least two strips of second circuit structure located on said substrate of said semiconductor wafer, each of said two strips of second circuit structure respectively linking the front end and the rear end of said plurality of strips of said first circuit structure. Pet (citing Ex. 1003, col. 1, ll ; col. 2, ll. 1 10; col. 3, ll ; Fig. 3; Ex , app. D 49 52). Petitioner asserts that, based on Evans s teaching of using chemical mechanical polishing (CMP) to remove all of the first insulating layer above the level of the nitride layer to form a structure, Evans teaches utilizing to average polishing pressure performed upon the front end and the rear end of 15

16 said plurality of strips of said first circuit structure during said chemical mechanical polishing process for reducing defects occurred. Id. at 32 (citing Ex. 1004, col. 3, ll ; Ex , 58 59, app. D 52). Petitioner contends that a person of ordinary skill in the art would have known that Yama s transistor could be fabricated using CMP because it was already well-known, widely-used, and understood to provide improvements to the fabrication process, and further, that person would have found it obvious and straightforward to apply CMP... to enjoy the predictable resulting benefits of CMP in connection with fabricating Yama s transistor. Pet (citing Ex ; Ex. 1001, col. 1, ll ; Ex. 1004, col. 3. ll ). In support of its contention of obviousness, Petitioner presents the following assertions: (1) both Yama and Evans concern the fabrication of integrated circuit devices, including transistors (citing Ex. 1003, col. 1, l. 53 col. 2, l. 26; Fig. 3; Ex. 1004, Abs.; col. 1, ll ; Ex ); (2) Yama discloses that its transistor could be fabricated using known fabrication techniques, which a person of ordinary skill in the art would have known to include CMP (citing Ex. 1003, col. 2, ll. 1 4; Ex , 58); and (3) a person of ordinary skill in the art would have turned to the prevalent fabrication techniques, known at the time of the invention, in the fabrication of known structures (citing Ex ). Id. On this record, there is not a reasonable likelihood that the combination of Yama and Evans teaches or suggests the claimed invention. Petitioner does not address sufficiently the functional language, addressed above in Section II.A., describing the second circuit structure as functioning to average the polishing pressure performed upon the front end and the rear 16

17 end of the plurality of strips of the first circuit structure during a CMP process. For example, Petitioner does not explain sufficiently how Yama s metal interconnection layer 3c and vertical portions of polysilicon gate 2 depicted in Figure 2 (i.e., second circuit structure), as modified by the teachings of Evans, inherently possesses the functionally defined limitations that is, a structure capable of averaging the polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during a CMP process. Therefore, based on the record before us, we determine there is not a reasonable likelihood that Petitioner would prevail on its assertion that claim 1 and dependent claims 2 8 would have been obvious over Yama and Evans. 3. Obviousness of Claim 5 Over Yama, Evans, and the Knowledge of a Person of Ordinary Skill in the Art, and Obviousness of Claim 6 Over Yama, Evans, and Fulford As applied by Petitioner, the knowledge of a person of ordinary skill in the art, and the teachings of Fulford, do not remedy the deficiencies of the combined teachings of Yama and Evans addressed above with respect to claim 1. See Pet , Accordingly, there is not a reasonable likelihood that Petitioner would prevail on its assertions that claim 5 would have been obvious over Yama, Evans, and the knowledge of a person of ordinary skill in the art, and that claim 6 would have been obvious over Yama, Evans, and Fulford. 17

18 III. PETITIONER S MOTION TO SEAL Petitioner moves to seal the unredacted version of the Petition (Paper 4), the unredacted version of Exhibit 1014, the entirety of Exhibit 1017, and the entirety of Exhibit Paper 6, 2. We do not rely on the information Patent Owner seeks to maintain as sealed. Therefore, Petitioner s motion to seal is dismissed as moot. For these reasons, we expunge the unredacted version of the Petition (Paper 4), the unredacted version of Exhibit 1014, and Exhibits 1017 and IV. CONCLUSION We conclude, based on the record before us, that there is a not a reasonable likelihood that Petitioner would prevail in showing that claims 1 8 are unpatentable. and Accordingly, it is: V. ORDER ORDERED that the Petition for inter partes review is DENIED; FURTHER ORDERED that Petitioner s Motion to Seal is dismissed; FURTHER ORDERED that Petitioner s unredacted version of the Petition (Paper 4), the unredacted version of Exhibit 1014, and Exhibits 1017 and 1019 shall be expunged from the record. 18

19 PETITIONER: J. Steven Baughman Steven Pepe ROPES & GRAY LLP PATENT OWNER: Michael M. Murray Andrew R. Sommer Michael J. Scheer WINSTON & STRAWN 19